| 摘要 |
A nonvolatile semiconductor memory device includes a plurality of floating gate type memory cell transistors, connected in parallel between a bit line and a source line and a plurality of floating gate type reference transistors. The reference transistors are arranged in a matrix, defining rows and columns. The memory cell transistors are arranged as a column in the matrix, such that one of the memory cell transistors is associated with a row of the reference transistors. A plurality of reference bit lines are connected to a respective drain of each of the memory cell transistors in a respective column. Each reference bit line has a capacitance different than the other reference bit lines, which allows multi-state information stored in the memory cell transistors to be determined in accordance with a dropping speed of the potential of the bit lines and plurality of respective reference bit lines.
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