发明名称 Design support system in which delay is estimated from HDL description
摘要 A design support device 1 has a module division and merger section 8 for receiving a result from a HDL analysis section 6 to analyze a HDL description of a RTL and for dividing and merging the modules based on instructions from outside or automatically, a module allocation section 10 for allocating the modules by using the result from the module division and merger section 8 and the analyzed result by the HDL analysis section 6, a budgeting section 11 for budgeting an area, a shape, a timing, and a power consumption to each of the modules allocated by the module allocation means 10, and an estimation section for estimating module information for the result from the module division and merger section 8 and the result from the module allocation section 10.
申请公布号 US5930147(A) 申请公布日期 1999.07.27
申请号 US19960724471 申请日期 1996.10.01
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 TAKEI, TSUTOMU
分类号 G06F17/50;(IPC1-7):G06F17/00 主分类号 G06F17/50
代理机构 代理人
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