发明名称 Semiconductor device, and method and apparatus for reducing a dead time in PWM inverter
摘要 In a PWM inverter having a two-arm structure of upper and lower arms, the dead time is reduced to a minimum for improving the controlling accuracy and linearity under a very small rate of the inverter power output. Also, in the PWM control on a motor, the controlling stability at a lower speed can be increased. Particularly, an improvement for use in a PWM inverter comprises off-state detecting means, each connected to a power switching element in one of the two upper and lower arms of the PWM inverter for detecting the off-state of the switching element and gate means, each provided for receiving an off-state detection signal fed back from the off-state detecting means of the opposite arm connected to the input of corresponding one of the two switching elements and generating a turn-on signal for the other switching element.
申请公布号 US5930132(A) 申请公布日期 1999.07.27
申请号 US19980114275 申请日期 1998.07.13
申请人 KABUSHIKI KAISHA WACOGIKEN 发明人 WATANABE, KAZUO;SATO, ATSUSHI
分类号 H03K17/73;H02M1/00;H02M1/38;H03F3/217;H03K17/00;H03K17/04;H03K17/16;(IPC1-7):H02M7/122;H02M1/12 主分类号 H03K17/73
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