发明名称 Asymmetric S/D structure to improve transistor performance by reducing Miller capacitance
摘要 A method of making a transistor is also disclosed, including the steps of forming a gate oxide layer (106) over a semiconductor substrate (100) and forming a gate structure (108) over a portion of the gate oxide layer (106), thereby separating the transistor into a first region (114) and a second region (112) with a channel region therebetween. The method also includes forming a source region (114) having a source LDD portion (116) and forming a drain region (112) having a drain LDD portion (124) in the second region (112), wherein the drain LDD portion (124) is more shallow than the source LDD portion (1 16). An asymmetric source/drain LDD transistor structure includes a semiconductor substrate (100), a gate oxide layer (106) overlying the substrate (100) and a gate structure (108) overlying the gate oxide layer (106). The transistor structure further includes a source region (129) and a drain region (128) formed in the semiconductor substrate (100) on opposite sides of the gate structure (108) which forms a channel region therebetween. A drain LDD region (124) is disposed between the drain region (128) and the channel and a source LDD region (116) is disposed between the source region (129) and the channel, wherein the drain LDD region (124) is more shallow than the source LDD region (116).
申请公布号 US5925914(A) 申请公布日期 1999.07.20
申请号 US19970944349 申请日期 1997.10.06
申请人 ADVANCED MICRO DEVICES 发明人 JIANG, CHUN;WU, DAVID DONGGANG
分类号 H01L21/336;H01L29/78;(IPC1-7):H01L29/76 主分类号 H01L21/336
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