发明名称 Semiconductor wafer, wafer alignment patterns
摘要 A semiconductor processing method of forming integrated cicuitry on a semiconductor wafer includes, a) forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective-series of elevation steps provided therein; and b) while fabricating integrated circuitry elsewhere on the wafer, processing a first portion of at least one of the alignment patterns differently from a second portion of the one alignment pattern to render the first portion to be different from the second portion in the one alignment pattern. Such preferably superimposes a secondary step, most preferably of the same degree, over only a portion of the elevation steps in at least one of the wafer alignment patterns. Further, a semiconductor processing method of forming integrated circuitry on a semiconductor wafer includes, i) forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective series of elevation steps provided therein; and ii) while fabricating integrated circuitry elsewhere on the wafer, processing one of the alignment patterns differently from the other to render the one alignment pattern to be different from the other alignment pattern.
申请公布号 US5925937(A) 申请公布日期 1999.07.20
申请号 US19970831529 申请日期 1997.04.01
申请人 MICRON TECHNOLOGY, INC. 发明人 JOST, MARK E.;HANSEN, DAVID J.;MCDONALD, STEVEN M.
分类号 G03F7/20;G03F9/00;H01L21/00;H01L23/544;(IPC1-7):H01L23/544 主分类号 G03F7/20
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