发明名称 A VERTICAL CONNECTOR BASED PACKAGING SOLUTION FOR INTEGRATED CIRCUITS
摘要 <p>An assembly featuring a substrate (940) and a plurality of components (900). The plurality of components are packaged to be connected in a vertical orientation to the substrate. These components include (i) a vertical chip scale package (CSP), (ii) an integrated circuit die (930) and (iii) an interconnect (950). Including a plurality of connection leads, the vertical CSP contains the die which is generally situated along a vertical plane. The interconnect, capable of transferring information between the plurality of connection leads and the integrated circuit die, includes a first segment generally perpendicular to the vertical plane and connected to at least one connection lead. The interconnect further includes a second segment generally in parallel to the vertical plane and connected to the integrated circuit die.</p>
申请公布号 WO1999035686(A1) 申请公布日期 1999.07.15
申请号 US1998027517 申请日期 1998.12.21
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