发明名称 |
Optimization apparatus which removes transfer instructions by a global analysis of equivalence relations |
摘要 |
The basic block division unit 2 divides the instruction sequence into basic blocks which are sequences with a continuous execution order. The control flow analysis unit 3 analyzes the control flow between basic blocks. The global equivalence relation analysis unit 4 traces the control flow between basic blocks and analyzes equivalence relations between resources, such as memory and registers, which cross over between basic blocks. The code is then optimized using these equivalence relations which cross over between basic blocks. In this way, the equivalence relations between resources in the program are analyzed globally and are used in the optimization of the code, so that a greatest possible reduction can be achieved in the code size and execution time of the program.
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申请公布号 |
US5923883(A) |
申请公布日期 |
1999.07.13 |
申请号 |
US19970815723 |
申请日期 |
1997.03.12 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
TANAKA, HIROHISA;SAYAMA, JUNKO;TANAKA, AKIRA |
分类号 |
G06F9/45;(IPC1-7):G06F9/45 |
主分类号 |
G06F9/45 |
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