发明名称 |
Multi-processor system and method for synchronizing among processors with cache memory having reset state, invalid state, and valid state |
摘要 |
In a multi-processor system including a plurality of processing units each having a cache memory, the processing units each include a synchronization counter for indicating a present synchronization state of the respective processing unit, and a cache state table for holding information regarding the respective entries of the cache memory. The cache state table includes a cache state and a cache synchronization count. The cache state holds the respective cache state used in a cache protocol. The cache synchronization count holds a value of the synchronization counter when an entry is loaded. A cache protocol in the multi-processor system is simplified to realize a high-speed processing.
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申请公布号 |
US5923855(A) |
申请公布日期 |
1999.07.13 |
申请号 |
US19960692346 |
申请日期 |
1996.08.05 |
申请人 |
NEC CORPORATION |
发明人 |
YAMAZAKI, TAKESHI |
分类号 |
G06F15/16;G06F12/08;(IPC1-7):G06F12/08;G06F15/163 |
主分类号 |
G06F15/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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