| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a moving image decoder where the capacity of a memory is reduced. SOLUTION: A decoder is provided with a coefficient reduction circuit 3 that eliminates half of coefficients for high frequency parts of horizontal frequencies among orthogonal transform coefficients in the unit of blocks of a prescribed size obtained from an input signal, an inverse orthogonal transform circuit 4 that obtains reproduced image data or time base predicted error data whose horizontal direction data are compressed to 1/2 in the unit of blocks by conducting inverse orthogonal transform through the use of the transform coefficients reduced by the coefficient reduction circuit 3, an adder 5 that produces reproduced image data whose horizontal direction data are compressed to 1/2 based on the time base predicted error data obtained by the inverse orthogonal transform circuit 4 and on prescribed reference image data, and a vertical interleave circuit 21 that interleaves the reproduced image data to 1/2 in the vertical direction obtained by the inverse orthogonal transform circuit 4 or the adder 5 to produce the reproduced image data whose horizontal and vertical direction data are respectively compressed to 1/2.</p> |
