发明名称 Method for achieving low capacitance diffusion pattern filling
摘要 An automated method for selectively locating fill pattern diffusion regions on a semiconductor substrate. In one embodiment, the present invention determines the locations of active diffusion regions on a semiconductor substrate. The present invention also determines the locations of interconnect lines on the semiconductor substrate. Next, the present invention creates a union of the location of the active diffusion regions on the semiconductor substrate and the location of the interconnect lines on the semiconductor substrate. The present invention uses this union to define allowable locations for placement of fill pattern diffusion regions on the semiconductor substrate such that the fill pattern diffusion regions are not disposed under the interconnect lines.
申请公布号 US5923947(A) 申请公布日期 1999.07.13
申请号 US19970851842 申请日期 1997.05.06
申请人 VLSI TECHNOLOGY, INC. 发明人 SUR, HARLAN
分类号 H01L27/02;(IPC1-7):G01R31/26;H01L21/66 主分类号 H01L27/02
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