| 摘要 |
<p>PROBLEM TO BE SOLVED: To improve the workability of bit lines by arranging the positioning pattern of a source impurity region and contact, to reduce the area of a cell array by reducing area other than effective cells in a NAND string, and to improve the accuracy of readout. SOLUTION: A drain impurities region 6b and a source impurities region 20 are formed in a semiconductor layer 4. Selected transistors S11, S12 and the like and memory transistors M11-M14 are connected in series in the row direction between the drain impurity region 6b and the source impurity region 20 to form a transistor row. The source impurities region 20 is separated from the source impurities region in another transistor row which is adjacent in the direction of the columns and is disposed in a line with other impurity regions 6a and 6b in the transistor row. A bit contact BC and a source contact SC are alternately disposed between the transistor rows which are adjacent in the column direction. A common source potential layer 22 which connects the source impurities regions 20 are disposed, for example in a planar form to shield a bit line BL 1 or the like of an upper layer in a direction vertical to the substrate.</p> |
