发明名称 MULTI-LAYER WIRING SUBSTRATE
摘要 PROBLEM TO BE SOLVED: To provide a multi-layer wiring substrate in which generation of any solder crack can be prevented at solder connection with a semiconductor part having a matrix-shaped electrode. SOLUTION: Connection pads 5, 6, and 7 formed corresponding to plural electrodes 3 of a semiconductor part 2 are formed with a difference in level, so that solder height of solders positioned between the electrodes 3 and the connection pads 5, 6, and 7 can be made gradually higher, according as they go from the connection pad 5 connected with the electrode 3 positioned in the center of an electrode formation face 2a toward the connection pad 7 connected with the electrode 3 positioned outside the electrode formation face 2a in this multi-layer wiring substrate.
申请公布号 JPH11186443(A) 申请公布日期 1999.07.09
申请号 JP19970354415 申请日期 1997.12.24
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 UEDA TAKASHI
分类号 H01L21/60;H01L23/12;H05K1/18 主分类号 H01L21/60
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