AUTOMATED DUAL SCATTER/GATHER LIST DMA

摘要

A DMA controller (100) useful in a host adapter (106) which adapts signals on its local bus (152) to those of a host system (104). The DMA controller of the present invention has two addressing engines each capable of operating on an independent scatter/gather list. A first addressing engine (200) in the controller is provieded with a first scatter/gather list for generating addresses on the host bus. The second addressing engine (220) in the controller is provided with a second scatter/gather list, independent of the first, for generating addresses on the local bus of the host adapter. A sequencer block (230) in the DMA controller coordinates the operation of the two DMA addressing engines so as to perform a DMA transfer. The descriptors in the independent scatter/gather lists need not be combined as previously known in the art to create a composite scatter/gather list wherein descriptors are created for the least common size of the corresponding source and destination descriptors. The DMA of the present invention thereby improves host adapter performance by reducing computation overhead in the host adapter's local processor required for generating the composite scatter/gather list and also permits each scatter/gather list to optimize block sizes for efficient burst transfers on the corresponding bus.