| 摘要 |
<p>In one aspect of the present invention, a bus buffer (32) is provided. The bus buffer (32) includes at least one buffer group (34) having first and second groups of control input terminals. The first and second groups of control input terminals control different operational characteristics of the buffer group. The bus buffer includes first and second capture registers (55 and 56) and first and second update registers (65 and 66). The data output terminals of the first update register (65) are connected to the first group of control input terminals. The data output terminals of the second update register (66) are coupled to the second group of control input terminals. The data input terminals of the first and second update registers (65 and 66) are coupled to the data output terminals of the first and second capture registers (55 and 56), respectively. The bus buffer (32) includes a new settings register (46) having data output terminals coupled to the data input terminals of the capture registers (55 and 56).</p> |
