发明名称 LATCH CIRCUIT AND DFF CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To prevent a feed through current of a latch part and to suppress an amplitude of a clock signal. SOLUTION: The first kind of inverters 31 and 32 are composed of a circuit which adds a feed through current prevention transistor and a clock transistor to a CMOS inverter circuit, the second kind of inverters 33 and 34 are connected to a following step, a gate of a clock transistor of the first kind of inverters 31 and 32 is connected to a clock terminal 38A and a gate of a feedback transistor MN32 connected so as to interpose the second kind of inverters 33 and 34 is connected to a clock terminal 38B. The gates of the feed through current prevention transistors of the first kind of inverters 31 and 32 are connected to an output side of the inverter of a rear step of the second step.</p>
申请公布号 JPH11177391(A) 申请公布日期 1999.07.02
申请号 JP19970351962 申请日期 1997.12.08
申请人 NEW JAPAN RADIO CO LTD 发明人 FUKUDA HIDEKI
分类号 H03K3/037;(IPC1-7):H03K3/037 主分类号 H03K3/037
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