| 摘要 |
<p>PROBLEM TO BE SOLVED: To save power consumption by preventing pass-through current which is intrinsic to a CMOS circuit from flowing, even when signal amplitude is not fully swung at the time of high speed operation, when load is high. SOLUTION: The through-current control terminals of inverters 11 and 12 are controlled by the output signals of the inverters 15 and 16 after four stages and also the through-current control terminals of the inverters 13, 14, 15 and 16 are controlled by the input signals of the inverters 11, 12, 13 and 14 before two stages. Therefore, when a delay time per inverter one stage is defined as tpd, through-current control terminal potential is inverted after 4tpd delay from an output inversion, its output signal forming circuit is interrupted and also a succeeding signal inversion circuit is formed in the inverters 11 and 12. Related the inverters 13-16, through-current control terminal potential is inverted, a previous-time output signal forming circuit is interrupted, a circuit prepared for the current inversion is formed and the input signal is inverted after 2tpd delay after that. Therefore, through-current occurrence in the inverters 11-16 is prevented, when 4tpd is set to <= a half of an input clock cycle.</p> |
