DYNAMIC TYPE RAM AND ITS OPERATING METHOD

摘要

PROBLEM TO BE SOLVED: To achieve a high-speed reading operation by resetting a start timing signal for generating a data transfer timing signal and generating the start timing signal by the back edge of an output signal for the output signal of a second address signal change detection circuit or thereafter. SOLUTION: A timing signal generation circuit DOEK1BG generates a timing signal DOEK1B by a signal ATCE only in the case of the first access under the conditions where a signal ATCE and a timing signal C1 formed by a/CAS system circuit included in a timing control circuit are at a high level. On the other hand, the other timing signal generation circuit DOEK2BG generates an address signal change detection signal ATCE being generated by a signal CE using an address signal change detection circuit ATD and a timing signal DOEK2B by an address signal change detection signal ATA being formed corresponding to the change in an address signal.