Viterbi decoding apparatus and viterbi decoding method

摘要

In a Viterbi decoder, a trace-back operation is carried out using three dual-port RAMs of the number of bits = 8 and the number of words = 4 are provided in a path memory circuit. Path selection information is sequentially written into the three RAMs every clock in accordance with the control of a control circuit. On the other hand, the path selection information is read out every clock from the RAMs in accordance with the control of the control circuit and is inputted as read path selection information or the like to a tracing circuit. The tracing circuit executes the tracing operation as many as three times on the basis of the read path selection information and trace starting state information which is formed by the control circuit. On the basis of a tracing result, the decoding data and a trace starting state in the subsequent clock are obtained. Thus, high speed operation is performed with a circuit having a small size. <IMAGE>