| 摘要 |
<p>A ferroelectric memory device is disclosed comprising a plurality of sets of bit lines connected to a plurality of memory cells each made up of one capacitor using a ferroelectric film and one MOS transistor, and a plurality of differential sense amplifiers that can be connected to the bit lines. The memory cells are each constructed such that the first electrode of the capacitor is connected to a plate line, the second electrode is connected to the source of the MOS transistor, the gate of the MOS transistor is connected to a word line, and the drain is connected to the bit line. The memory cells generate a reference voltage, and the sense amplifiers sense memory cell data using the self-generated reference voltage as a standard. <IMAGE></p> |
