发明名称 Self-test and correction of loss of charge errors in a flash memory, erasable and programmable by sectors thereof
摘要 <p>A method of self-test and correction of errors due to a loss charge for a flash memory constituted by an array or matrix of cells (bits), organized in rows and columns, erasable and programmable by whole sectors in which the matrix is divided, implemented by realizing at least an additional row and at least an additional column of cells for each memory sector; storing parity codes is the additional row and column, and carrying out periodically a self-test routine and eventual correction routine composed of the following steps: repeating the sequential reading per bytes and parity check; verifying the consistency of the parity value with the value stored in the respective parity bit; if the verification is negative, retaining the current row address and proceeding to sequentially verify column parity starting from the first column until identifying the column for which the verification yields a negative result, and if the failed bit so individuated is "1" reprogramming it to "0".</p>
申请公布号 EP0926687(A1) 申请公布日期 1999.06.30
申请号 EP19970830693 申请日期 1997.12.22
申请人 STMICROELECTRONICS S.R.L. 发明人 CAPPELLETTI, PAOLO;MAURELLI, ALFONSO;OLIVO, MARCO
分类号 G11C16/06;G06F11/10;G11C29/00;G11C29/06;G11C29/52;(IPC1-7):G11C29/00 主分类号 G11C16/06
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