发明名称 |
Integrated multi-layer test pads |
摘要 |
A multi-layer test pad on a semiconductor wafer, which includes an underlying matrix of interconnected first pads, which are arranged in rows and columns. The multi-layer test pad includes an oxide layer disposed above the underlying matrix and in between the rows and columns. The multi-layer test pad further includes an overlying matrix of interconnected second pads disposed above the oxide layer. Each of the second pads completely overlaps at least nine of the first pads, including four oxide regions surrounding a center first pad of the nine of the first pads. The nine of the first pads are arranged as 3x3 block of the first pads.
|
申请公布号 |
US5917197(A) |
申请公布日期 |
1999.06.29 |
申请号 |
US19970861465 |
申请日期 |
1997.05.21 |
申请人 |
SIEMENS AKTIENGESELLSCHAFT;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ALSWEDE, FRANK;DAVIES, WILLIAM;HOYER, RONALD;MENDELSON, RON;PREIN, FRANK |
分类号 |
H01L21/66;H01L23/58;(IPC1-7):H01L23/58 |
主分类号 |
H01L21/66 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|