Method for fabricating capacitor-over-bit line (COB) dynamic random access memory (DRAM) using tungsten landing plug contacts and Ti/TiN bit lines

摘要

A method and structure are described for making DRAM devices having bit line contacts for memory cells and landing plugs for peripheral devices with a Ti/TiN barrier layer patterned to form bit lines and local interconnections. FETs are formed on the substrate for memory cells and for devices in the peripheral area. A planar first insulating layer is deposited, and contact openings are formed to the devices. A Ti/TiN barrier layer is deposited in the contact openings and a tungsten (W) layer is deposited and selectively etched back to the barrier layer. The barrier layer is then patterned to form bit lines and local interconnections. A second insulating layer is deposited, and capacitor node contact openings are etched and filled with polysilicon to form node contacts on which capacitors are fabricated. A planar third insulating layer is formed and multilevel contact openings are etched to landing plugs. Metal plugs are formed in the multilevel contact openings, and a first metal is deposited and patterned to form the first level of metal interconnections. The reduced height of the Ti/TiN bit lines and the landing plug contacts significantly reduce the aspect ratio of the multilevel contacts, allowing for fabricating DRAM circuits with higher density and improved reliability.