发明名称 |
Method for manufacturing a CMOS self-aligned strapped interconnection |
摘要 |
An CMOS interconnection method that permits small source/drain surface areas has been provided. The interconnection is applicable to both strap and via type connections. The surface areas of the small source/drain regions are extended into neighboring field oxide regions by forming a silicide film from the source/drain regions to the field oxide. Interconnections on the same metal level, or to another metal level are made by contact to the silicide covered field oxide. The source/drain regions need only be large enough to accept the silicide film. Transistors with small source/drain regions have smaller drain leakage currents and less parasitic capacitance. A CMOS transistor interconnection apparatus has also been provided.
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申请公布号 |
US5915199(A) |
申请公布日期 |
1999.06.22 |
申请号 |
US19980090802 |
申请日期 |
1998.06.04 |
申请人 |
SHARP MICROELECTRONICS TECHNOLOGY, INC.;SHARP KABUSHIKI KAISHA |
发明人 |
HSU, SHENG TENG |
分类号 |
H01L21/28;H01L21/285;H01L21/3205;H01L21/768;H01L21/8238;H01L27/092;(IPC1-7):H01L21/476 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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