发明名称 ERROR SYNCHRONOUS DETECTION CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To improve the rate of input-output ports and to perform plural processing in a system by writing only a frame that is decided as synchronous as a result of the frame synchronous decision of input data in a buffer and accumulating synchronous establishment frames. SOLUTION: Input data to input ports 11 and 12 are inputted to buffers 14 and 15 and when data are accumulated equally or more than certain threshold, threshold detection flags 22 and 23 are outputted. Also, input data to an input port 13 is inputted to a gate circuit 32 and a frame header detection circuit 31. If a synchronous establishment frame exists as a result of synchronous detection in the circuit 31, a control signal 33 that shows frame validity is given to a buffer 16 through the circuit 32. When the buffer 16 accumulates data equally or more than certain threshold, it outputs a threshold detection flag 35. A CPU processing part 17 performs processing of the flags 22, 23 and 35, being aware of frames and because there is no frame error synchronous detection, the appropriation of partial data processing time becomes unnecessary for synchronous processing and it becomes possible to improve the rates of input-output ports 11 to 13 and 18.</p>
申请公布号 JPH11163843(A) 申请公布日期 1999.06.18
申请号 JP19970325936 申请日期 1997.11.27
申请人 OKI ELECTRIC IND CO LTD 发明人 EGUCHI KOHEI
分类号 H04L1/00;H04L7/00;H04L7/08;(IPC1-7):H04L7/00 主分类号 H04L1/00
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