| 摘要 |
PROBLEM TO BE SOLVED: To reduce the test time of DC characteristics of a semiconductor integrated circuit, and shorten a pattern for DC characteristics test. SOLUTION: In an LSI which is logic-designed by using a combined circuit 0 and D flip-flop's 1-12, the D flip-flop's are substituted by scan type flip-flop's 1-12 which can switch the ordinary data input/output and the scan data input/ output by a mode selection signal supplied from an external connection terminal. After the scan type flip-flip's 1-12 are connected by using a scan chain (p), they are divided into every four, between which D flip-flop's 13-1 to 13-4, 14-1 to 14-3 capable of setting the initial state are inserted. The D flip-flop's 13-1 to 13-3 are initially set in the state '0', and the D flip-flop's 14-1 to 14-3 are initially set in the state '1'. |
