| 摘要 |
PROBLEM TO BE SOLVED: To decode a veritable length code at a high speed, without the use of higher clock frequency for the processor. SOLUTION: This processor is configured with a shift circuit 3, that receives input code strings coupled with common data bus lines and shifts data having been decoded, an arithmetic circuit 4 that obtains a shift amount of the shift circuit 3, the common data bus lines that connect the circuits 3, 4 and a general- purpose register 6, an exclusive line 105 through which the variable length code read from the shift circuit 3 is outputted to a variable length code table 13 which outputs a decoded value and a code word length of the variable length code, and an exclusive line 106 through which the code word length is outputted to the arithmetic circuit 4. Thus, the operation of decoding the variable length code and storing the result to a register or the like and the operation of shifting the code strings by the code number, and calculating the shift number of the code to output a succeeding code can be executed concurrently. |
