发明名称 SIGNAL GENERATING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a signal generating circuit improved in spurious suppression performance and capable of using a PLL circuit realized with a small capacitance. SOLUTION: A PLL circuit 15 suppresses a spurious component generated by a DDS circuit and a C/A converter 2. An output from a phase comparator 4 of a PLL circuit 15 is distributed into two paths, the one component is used to apply frequency control to a VCO via gain control and the other component is used to apply frequency control to the VCO via a primary filter so as to act a circuit processing the one component like a lead filter and to act a circuit processing the other component like a lag filter. The gain and the time constant of the primary filter are changed depending on color or black/white discrimination to improve the suppression performance and to reduce a capacitance of an integration capacitor C.
申请公布号 JPH11150735(A) 申请公布日期 1999.06.02
申请号 JP19970313914 申请日期 1997.11.14
申请人 TOSHIBA CORP 发明人 MURAYAMA AKIHIRO
分类号 H04N9/45;H03L7/08;H03L7/107 主分类号 H04N9/45
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