| 摘要 |
The invention relates to a RAM memory cell (10) for a memory matrix comprising a plurality of word-lines (WL) and bit-lines (BL), said cell (10) including a first and a second cross-coupled CMOS inverters (12, 13), each including a PMOS pull-up transistor (M3, M4) and an NMOS pull-down transistor (M1, M2), and first and second access transistors (M5, M6) connecting the second (13) and the first inverter (12) to a corresponding bit line respectively, characterized in that the source terminals of the pull-down transistors (M1, M2) are connected to a precharge line (PL) running parallel to each word line. Moreover, the first and second access transistors (M5. M6) are PMOS transistors having their gate terminals connected to the word line (WL). <IMAGE> |
