| 摘要 |
PROBLEM TO BE SOLVED: To provide the parity arithmetic circuit that designates a normal parity arithmetic range in a 1st parity arithmetic operation after recovered from out of synchronism in a synchronization transmission system. SOLUTION: Through the adoption of a shift register 6 that has a bit number depending on a difference between a head position of a frame and a position of a frame synchronization pattern and a parallel parity arithmetic section 7, horizontal parity is calculated from the head of a frame to a concerned position in synchronization detection timing. In the case of detecting the synchronization during counter stopping, normal parity arithmetic operation is conducted by replacing an arithmetic value in an erroneous range calculated continuously from a head of the frame before going out of synchronism with the arithmetic value in the normal range from the head of the frame whose synchronization is recovered. |
