CLOCK STOP SIGNAL GENERATION CIRCUIT FOR LSI

摘要

PROBLEM TO BE SOLVED: To provide a clock stop signal generation circuit for an LSI capable of shifting the LSI into a low power consumption mode without needing a dedicated external pin or an internal register. SOLUTION: This circuit 10 monitors the states of more than two signals S1 to SN which are separately inputted from an input pin or a directional pin in an input state, detects whether or not all of more than two signals S1 to SN stop for more than a prescribed fixed time and generates a sleep flag SLP in accordance with it to control the operation or stop of an internal clock signal that is supplied to an internal circuit in accordance with the state of the sleep flag SLP.