| 摘要 |
PROBLEM TO BE SOLVED: To improve a bit error rate by correcting a bit error with respect to 1st bus data of a filter output, which is performed band limitation by means of maximum likelihood series decision by Viterbi algorithm. SOLUTION: A bus allocating circuit 11 divides I and Q data 4 and 5, which are performed band limitation into 1st bus data 12 and the other data 13, inputs the data 12 into a 4-ary differential converting part 14, inputs 1st bus data 16 subjected to differential conversion to a Viterbi algorithm series estimating device 22 and performs series estimation of the 1st bus. Meanwhile, the data 13 except the 1st bus data is inputted to a differential converting part 15, an output 17 which is subjected to binary differential conversion is inputted to a delay adjusting circuit 23 and a delay that is equivalent to the device 22 is given. A 1st bus series estimation result 24 subjected to bit error correction and a delay adjustment result 25 of the circuit 23 are inputted to a bit composing circuit 18 and bus data are reconstructed at I and Q data 20 and 21. |
