| 摘要 |
PROBLEM TO BE SOLVED: To reduce no. of main bit lines to relax wiring design rules by sharing bank select lines with bank select transistor pairs to make auxiliary conductive regions common between adjacent bank regions. SOLUTION: On a semiconductor substrate sub-bit lines SB11-SB27 are wired in the column direction, and word lines WL001-WL232 are wired in the row direction crossing the sub-bit lines SB11-SB27 with bank cells BT11-BT28 formed between the sub-bit lines SB11-SB27 and auxiliary conductive regions BB1, BB2. The bank cells BT15, BT25 use a bank select line BS13 as a common gate electrode, the bank cells BT16, BT26 use a bank select line BS 14 as a common gate electrode and the bank cells BT17, BT27 use a bank select line BS24 as a common gate electrode, and the bank cells BT18, BT28 set bank selected line BS33 as a common gate electrode respectively. |
