HOCHLEISTUNGSMANTISSENDIVIDIERER.

摘要

A high performance floating point mantissa divider employs SRT division, a Radix-4 redundant digit set and the principles of carry-save addition. At each step in the division, the upper few most significant bits of the partial remainder and the divisor are inspected via a look-up table to select the appropriate quotient digits. The quotient digits are represented in a Radix-4 redundant digit set, and the look-up table is generated using SRT division principles. The selected quotient digit is used to control a multiplexor which selects the selected multiple of the divisor. This value is subtracted from the partial remainder via a carry-save adder to form the new partial remainder. As the quotient digits are generated, they are placed in two shift registers, one for the sum digits and one for carry digits. When the division is complete, the shift registers are added to give the final quotient mantissa. A combination of a carry save adder and carry look ahead adder reduce the practical implementation to only 8 logic levels.