| 摘要 |
In a normal mode, a logic test signal (LOGTEST), a RAM test signal (RAMTEST), and a shift mode signal (SM) are set to "0". A RAM core (91) is synchronously written and asynchronously read. In a logic test mode, the RAM test signal (RAMTEST) is set to "0", and the logic test signal (LOGTEST) is set to "1". In a RAM test mode, the RAM test signal (RAMTEST) is set to "1", and the logic test signal (LOGTEST) is set to "0". A scan path (3a) is used both as a scan path provided between logic portions (82, 83) in the logic test and as a scan path provided at the output of the RAM core (91) in the RAM test. The scan path provides a high area utilization efficiency.
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