发明名称 |
Synchronous semiconductor device having circuitry capable of surely resetting test mode |
摘要 |
A reset signal generating circuit in a synchronous semiconductor memory device outputs a reset signal ZPOR1 in response to a power on reset signal ZPOR generated immediately after power on and an initialize command (for example, a precharge command) executed for initialization after power on. A test mode register included in a mode setting circuit receives as a reset signal, the reset signal ZPOR1. Consequently, a test mode signal output attains to an NOP state, or output of the test mode signal is stopped. |
申请公布号 |
US5905690(A) |
申请公布日期 |
1999.05.18 |
申请号 |
US19980058987 |
申请日期 |
1998.04.13 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
SAKURAI, MIKIO;TANIDA, SUSUMU;TSUKIKAWA, YASUHIKO;NAKANO, MASAYA;FUKIAGE, TAKAHIKO |
分类号 |
G11C11/407;G01R31/317;G11C11/401;G11C29/14;(IPC1-7):G11C8/00 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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