| 摘要 |
This invention concerns a device for supplying a clock signal (clock) in a telecommunications system with a time division multiplexed data bus consisting of a working clock generating device (A) (working clock supply) for a working clock output signal (CLK 1) and a redundant protection clock generating device (B) for a protection clock output signal (CLK 2), with the two output clock signals (CLK 1, CLK 2), each being applied in parallel to bus interface units, and switching means are provided for reversible switching between the working clock output signal (CLK 1) and the prot ection clock output signal (CLK 2). To prevent bit errors in the transition between two clock signals from different clock generating devices, phase difference detecting means (phase detectors) are provided for detecting the phase difference ( DELTA phi 0) between the working clock output signal (CLK 1) and the protection clock output signal (CLK 2), which are connected to delay means (delay lines 1-6) such that the front edge of the output signal (CLK 1, CLK 2) taking over the clock function after switching can be delayed by at least a period of time ( DELTA phi 1), such that it is in the range (II) of undisturbed data bits, outside the time division multiplexed operation marginal range (I) (timing marginal). |
