DISTRIBUTED COMPLETION CONTROL IN A MICROPROCESSOR

摘要

The distributed completion mechanism maintains complex control dependence relations between instructions in a superscalar processor without the cycle time burden associated with large sequential queue structures. There are global busses, but none of them are cycle limiting (in general, they are almost latch-to-latch paths). The cost of this completion control mechanism is a large number of tag bits associated with each instruction stage, however, in light of shrinking lithography this cost is small and takes advantage of the strengths of newer technologies.