| 摘要 |
A processor (100) is provided with a datapath (102) and control logic (104) to control the datapath to selectively execute a number of hierarchically organized primitive operations to effectuate execution of user instruction streams constituted with instructions of the ISA. In one embodiment, primitive operations are statically organized into atomic units (112), which in turn are statically organized into snippets (114) of execution threads. Selected ones of the snippets are logically associated together to form execution threads (116), which collectively implement the instructions of the ISA. In one embodiment, the datapath employs cache memory (1002) based execution. In one embodiment, the cache memory emulates virtual register sets (1204). In one embodiment, the datapath control logic includes a primary control unit (PCU) (150) and at least one other auxiliary control unit (ACU) (152). In one embodiment, one of the ACU is an adaptable I/O control unit. |
