| 摘要 |
Embodiments of the invention include a dynamic random access memory (DRAM) and method for making a DRAM in which the capacitive elements are fabricated to be planar or nearly planar and to be located above the metal regions (M1) that connect the sources and drains of the transistor through conductive windows (W1). Embodiments of the invention fabricate the DRAM by forming a transistor on a suitable substrate in the appropriate manner and depositing a first oxide layer that is subsequently planarized by suitable technique. A window is then formed within the oxide layer and a conductive plug is formed within the window. A first patterned metal region, which functions as a memory cell bit line or as a coupler between conductive plugs, is then formed on the oxide layer. A second oxide layer is formed thereon and appropriate windows and conductive plugs are formed therein. Then, a capacitor is formed thereon in a planar or near planar configuration. A second patterned metal region is formed on the capacitor. A third oxide layer is formed thereon and appropriate windows and conductive plugs are formed therein. A third patterned metal region is then formed on the oxide layer. Finally, a fourth oxide layer is deposited and planarized in an appropriate manner. Alternatively, a trench is formed within the second oxide layer around the conductive plug prior to formation of the capacitor thereon. Also, in alternative embodiments, conductive plugs are coupled without the use of patterned metal regions. According to embodiments of the invention, the DRAM fabrication method and the DRAM formed thereby are more conducive than conventional fabrication methods to the use of planarization techniques such as chemical mechanical polishing (CMP). The planar or near planar configuration of the various oxide layers and various DRAM elements formed therein lend themselves well to planarization techniques.
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