发明名称 Packet handler
摘要 A packet handler includes an interface circuit of an ATM handler corresponding in one-to-one relation to each input/output port of an ATM switch. A switch interface including a disconnection circuit and a distribution circuit controls the cell flow from each interface circuit to a corresponding input port and the cell from the output ports of the ATM switch to each interface circuit. In a set of interface circuits, one redundant transmission path can be replaced arbitrarily with two nonredundant independent transmission paths. The ATM communication system can thus accommodate redundant transmission paths and nonredundant transmission paths in an arbitrary ratio.
申请公布号 US5903544(A) 申请公布日期 1999.05.11
申请号 US19970826523 申请日期 1997.04.03
申请人 HITACHI, LTD. 发明人 SAKAMOTO, KEN'ICHI;SHINOHARA, YASUNARI;KOZAKI, TAKAHIKO
分类号 H04L1/22;H04L12/56;H04Q3/00;H04Q11/04;(IPC1-7):H04J1/16;H04J3/14 主分类号 H04L1/22
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