| 摘要 |
A multiplier architecture (Fig. 5) in accordance with the present invention provides increased operating speed, and yet maintains regularity in its structure (Figs. 3, 12 or 13) in order to achieve a small floor plan (Fig. 4) when reduced to silicon. A Hekstra-type multiplier is modified by replacing many of the full adders circuits (F) with compressor circuits (C; Figs. 8-11) in a manner that preserves the balance of the signal delays between the various propagation paths through the summing stages (SA, MS). The result is an architecture having a regular layout that greatly facilitates its implementation in silicon.
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