发明名称 |
Decoder circuit using redundancy signal having a short pulse format |
摘要 |
Disclosed is a decoder circuit including: a redundancy section row decoder for responding a redundancy main word line signal, thereby selecting a redundancy section word line; a normal section row decoder for receiving a redundancy signal and a normal main word line signal applied from a row redundancy address decoder, thereby selecting a section word line; and, a row redundancy address decoder for generating a signal having a pulse width up to before a next cycle following a redundancy cycle as a redundancy signal, thereby providing the signal to the normal section row decoder and providing the redundancy main word line signal to the redundancy section row decoder during the redundancy cycle, in response to a clock transiting in the redundancy cycle.
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申请公布号 |
US5901106(A) |
申请公布日期 |
1999.05.04 |
申请号 |
US19970961049 |
申请日期 |
1997.10.30 |
申请人 |
SAMSUNG ELECTRONICS, CO., LTD. |
发明人 |
CHUNG, MIN-CHUL;KIM, JONG-YOUNG |
分类号 |
G11C11/413;G11C11/401;G11C29/00;G11C29/04;(IPC1-7):G11C8/00 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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