Low voltage ECL latch and flip-flop

摘要

An ECL latch circuit eliminates a transistor in a latch driver, thereby reducing the operating voltage required for the latch. The latch includes an input circuit having a differential pair of transistors which is coupled directly to a current source. A data latch is coupled to the input circuit, and a latch driver is coupled between the data latch and the current source. The latch circuit is driven with a single-ended clock signal which has a bias level that is higher than the bias level of a pair of complimentary data input signals. This causes the differential pair of transistors in the input circuit to turn off when the latch driver activates the data latch circuit. The data latch includes a differential pair of transistors coupled to latch a pair of complimentary data output signals. The latch driver includes a single transistor coupled to activate the data latch responsive to a single-ended clock signal. An ECL flip-flop circuit utilizes a pair of ECL latches, each of which has a differential pair of transistors which is coupled directly to a current source. The latches are connected in a master-slave configuration with a signal generator disposed between the two latches for generating the data input and clock signals for the slave latch responsive to the data output signals from the master latch.