发明名称 Power supply wiring for semiconductor device
摘要 <p>Ground lines 2 are disposed so as to sandwich a power supply line 1. A gate oxide film 3 and a gate 4 are formed below the power supply line 1. An n-type area 8 is formed adjacent to the end of the gate oxide film to set the ground potential thereto. A p-type area 9 is formed at most of the remaining part below the ground line to make it contact the substrate. Since the potential of the gate equals that of the power source, an inversion layer is formed below the oxide film, where the ground potential results through the n-type area. By sandwiching the gate oxide film between the gate and the inversion layer, a capacitor is formed. The size of the capacitor is half in length as large as the width of the power supply wiring, and the width substantially equals the length of the power supply wiring, the parasitic resistance generated at the gate or inversion layer is suppressed small, and the gate capacitance approximately corresponding to the area of master power supply wiring is interposed between the power source and the ground. As a result, a large capacitance bypass capacitor can be formed between the power source and the ground, and a power supply wiring which is great in effect of eliminating power supply noise can be obtained. <IMAGE></p>
申请公布号 EP0644594(B1) 申请公布日期 1999.04.28
申请号 EP19940114310 申请日期 1994.09.12
申请人 NEC CORPORATION 发明人 SUZUKI, KAZUMASA
分类号 H01L21/82;H01L21/822;H01L23/528;H01L27/02;H01L27/04;(IPC1-7):H01L23/50 主分类号 H01L21/82
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