| 摘要 |
PROBLEM TO BE SOLVED: To optimize the relation between the input end of serial data and the output timing of parallel data by processing a strobe signal in the serial- parallel converting circuit in parallel to latch operation for the serial data. SOLUTION: In the serial-parallel converting circuit, circuits 18 and 19 are added which latch a flag signal FLAG with timing pulses used for serial-parallel converting operation. Consequently, a data strobe signal DS can be outputted in the timing tDS where flip-flops of the following stage finish latching all the serial data. The delay time that a flip-flop 19 requires for latching is as long as the delay time needed for the latching of the flip-flops 14 to 17, so the data strobe signal DS has the shortest most accurate timing tDS. Therefore, normal serial data Dn to Dn+3 can be outputted in more suitable timing in parallel. |
