发明名称 COMPUTER SYSTEM
摘要 <p>PROBLEM TO BE SOLVED: To greatly reduce the power consumption by placing an MPU in fast operation without stopping a clock when the process load on the MPU is heavy and stopping the clock for as a long time as possible when the load is light. SOLUTION: The MPU 1 outputs a register update signal S1 indicating whether or not a register has been updated and a stall signal S2 indicating whether or not the MPU 1 is in a stall state. The value that a register update frequency counter 106 holds is increased or decreased, or held as it is according to the signals S1 and S2. A clock stop inhibition part 105 decides the process load on the MPU 1 by using the count value. According to the decision result, a clock supply control part 102 controls the clock supply to the MPU 1.</p>
申请公布号 JPH11110063(A) 申请公布日期 1999.04.23
申请号 JP19970266961 申请日期 1997.09.30
申请人 TOSHIBA CORP 发明人 MATOBA TSUKASA
分类号 G06F15/78;G06F1/04;(IPC1-7):G06F1/04 主分类号 G06F15/78
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