METAL STAPLES TO PREVENT INTERLAYER DELAMINATION

摘要

The present invention provides in one embodiment thereof an integrated circuit (IC) that includes silicon substrate. The integrated circuit includes a plurality of dielectric and metal layers formed upon the silicon substrate. The plurality of dielectric and metal layers form a die active area (501). The metal have formed therein a first guard wall (508) surrounding the die active area. The metal layers further have formed therein a second segmented guard wall. The segments guard wall surrounds and staples the plurality of metal layers (M1, M2, M3, M4, M5). The IC also includes a passivation layer adhering to the first and the segmented guard walls.