Semiconductor device with DRAM cell and peripheral circuit areas

摘要

A semiconductor device has a DRAM cell area and a peripheral or logic circuit area. Silicide layers are provided on the peripheral circuit MOS transistor gate electrodes and source/drain regions. The peripheral circuit MOS transistor gate electrodes have a sidewall insulation material which is also deposited on the gate electrodes and source/drain regions of the MOS transistors forming the memory cells in the DRAM cell area. Independent claims are also included for: (i) a similar semiconductor device in which storage nodes are electrically connected to one of the source/drain regions (7) of the MOS transistors in the memory cell area (1), a dielectric layer and a cell plate are applied on the storage node surfaces and silicide layers are formed on the MOS transistor gate electrode (6) surfaces and the surface of the other source/drain region (7) in contact with a bit line contact (12); (ii) a semiconductor device with an MOS transistor formed in a DRAM cell area (1) of a semiconductor substrate (3), storage nodes electrically connected to one of the source/drain regions (7) and a dielectric layer and a cell plate on the storage node surface, the novelty being that a silicide layer is applied on the cell plate surface and an interlayer insulating layer (11) and an upper conductor are formed on the silicide layer; and (iii) the production of the above devices;