发明名称 Low power bias circuit using FET as a resistor
摘要 A circuit is provided which generates a reference bias current using a difference in base-emitter voltages of two bipolar transistors imposed across a source terminal and a drain terminal of an MOS transistor. The circuit includes a circuit for compensating shifts in threshold voltage, and thus shifts in the current flowing therein, of the MOS transistor. In one embodiment, the bias circuit is configured to achieve superior efficiency in generating small bias currents. In another embodiment, the bias circuit is configured to operate using minimal voltage supplies. In all embodiments, the reference bias current generated thereby has a positive temperature coefficient and is substantially independent of process variations.
申请公布号 US5892388(A) 申请公布日期 1999.04.06
申请号 US19960632781 申请日期 1996.04.15
申请人 NATIONAL SEMICONDUCTOR CORPORATION 发明人 CHIU, KWOK-FU
分类号 G05F3/20;G05F3/26;(IPC1-7):G05F1/10;G05F3/02 主分类号 G05F3/20
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