Frequency domain kernel phase processor

摘要

A frequency domain kernel phase processor comprises an input buffer to store Fourier coefficients input from a Fourier transform of a communications signal. A communications signal suitable for processing by the present invention typically comprises a desired signal masked by a stronger interference signal having varying power that spans a range of frequency bins encompassing the desired signal. A scheduler inputs Fourier transform coefficients from the input buffer and generates a series of magnitude squares and symmetric phase differences for each frequency bin. The magnitude squares and the symmetric phase differences are output to phase transform processors which transform the symmetric phase differences to reveal the desired signal. The transformed outputs from the phase transform processors are output to an output buffer to be formatted and displayed.